The present invention relates to an apparatus for pipe latch control circuit in a synchronous memory device.
The most prominent issue of the semiconductor memory field is a synchronous memory device such as SDRAM, DDR, double data rate SDRAM and RAMBUS DRAM. Synchronous memory is advantageous in that the operation is fast compared to general memory devices.
In synchronous memory devices such as the DDR SDRAM, a pipeline method is applied to most of the data buses. FIG. 1 is a block diagram of a synchronous memory data path utilizing an ordinary pipeline method in accordance with the prior art.
In FIG. 1, the synchronous memory data path includes: four pipe latches 14A through 14D, a first switch 12 for selectively passing output data, which is applied from a global data bus gio to one of the pipe latches by pipe input control signals pinz less than 0:3 greater than , a data output buffer 18 for outputting the data to a data output terminal DQ using a data output buffer drive signal clk_do and a second switch 16 for selectively passing each output of the pipe latches 14A through 14D to the data output buffer 18 by pipe output control signals poutz less than 0:3 greater than .
Furthermore, in the above synchronous memory data path, the pipe output control signals poutz less than 0:3 greater than  are provided for controlling the output of the pipe latches 14A through 14D and they come from a pipe latch control circuit 10, which inputs an output enable signal outen and a DLL clock signal clk_dll.
Meanwhile, the pipe latch 14A is divided into an even path and an odd path in the DDR SDRAM, because the global data bus gio is divided into an even data bus and an odd data bus. Furthermore, the pipe latch control circuit 10 is classified into even and odd parts.
FIG. 2 is a circuit diagram of the pipe latch control circuit in accordance with the prior art.
In FIG. 2, the pipe latch control circuit is reset by a reset signal rstdoutz and starts counting when an increment signal outeninc is received.
However, the pipe latch control circuit includes an initial counting controller 20 for generating an initial counting signal. The rest of the units form four stage counters. Each counting stage includes a transfer gate controlled by the increment signal, an inverter latch and an ordinary counter.
FIG. 3 is a timing chart of the pipe latch control circuit shown in FIG. 2 in accordance with the prior art. In FIG. 3, let the burst length BL be 4 when using the SDRAM and the burst length BL be 8 when using the DDR SDRAM.
In the pipe latch control circuit in accordance with the prior art, the increment signal outeninc is generated by performing a NAND operation on the output enable signal outen and the DLL clock signal clk_dll. That is, the increment signal outeninc is generated by receiving the DLL clock signal clk_dll during the active cycle of the output enable signal outen. The output enable signal outen forms a window as much as the burst length for the data outputting the data.
The increment signal outeninc controls the transfer gate in order to output count signals k less than 0:3 greater than  through the latch. The count signals k less than 0:3 greater than  pass through three inverters to generate the pipe output control signals poutz less than 0:3 greater than . That is, the pipe output control signals poutz less than 0:3 greater than  are enabled by synchronizing with a falling edge of the increment signal outeninc.
However, the DLL clock signal clk_dll passes through eight gates before the pipe control signals poutz less than 0:3 greater than  appear as in FIG. 2. Actually, the data output buffer drive signal clk_do for controlling the data output from a DQ pin is a delayed signal compared with the DLL clock signal clk_dll. Therefore, the data output buffer drive signal clk_do is enabled so that the data is outputted from the data output buffer within the enabling period of the pipe output control signals poutz less than 0:3 greater than  under normal conditions. However, the data output buffer drive signal clk_do receives the DLL clock signal clk_dll during the activation of the output enable signal outen.
However, the operation timing of all semiconductor circuits is greatly changed according to whether an operation condition is the best condition or the worst condition. In the prior art as mentioned above, after the DLL clock signal clk_dll is disabled, since the pipe output output control signal poutz less than 0:3 greater than  is generated by passing through 8 gates, a long delay time is caused. Specifically, a considerable difference of the delay time between the best condition and the worst condition can occur. Accordingly, in case of the worst condition, the corresponding data from the data output buffer may not be outputted completely within the enabling period of the pipe output control signals poutz less than 0:3 greater than . Therefore, the memory access time TAA should be limited for the complete data output. As an operation frequency increase, a loss of the memory access time TAA can be a serious problem.
It is, therefore, an object of the present invention to provide an apparatus for a pipe latch control circuit in a synchronous memory device.
In accordance with an aspect of the present invention, there is provided an apparatus for a pipe latch control circuit controlled by a pipe output control signal in a synchronous memory device, comprising: a plurality of counting stages for counting in sequence in response to a data output buffer drive signal; and a counting signal drive means for generating the pipe output control signal by driving each counting signal, which is outputted from the plurality of counting stages and controlled by the data output buffer drive signal.